We are looking for Verification Architect to SoC DU organization
We are looking for an engineer with an architect level of experience in RTL verification activities. An engineer who can: define verification strategies and methodologies for projects; plan, coordinate and lead verification people; efficiently utilize System Verilog and UVM in test environment, reuse and VIP development; guide, teach and support less experienced verification engineers in debugging our SoC or IP design and architectures, e.g. in Digital Radio Front End (DFE) area. A person who can lead verification architecture topics in our Digital Front End SoC activities.
You have a hungry mind to learn more and you are excited doing a variety of different kinds of design and verification tasks as part of your job. You are always ready to share your knowledge and skills among the people you work with. You are a team worker but also efficient on independent tasks, and your English language skills allow you communicate efficiently in our multicultural environment. You have a passion to develop the best possible verification architecture and ability to establish realistic intermediate steps to achieve the same in phases.
Main Responsibility Area
As a member of SoC DU organization you will participate to verification architecture definition as your main responsibility area. Main responsibilities include: specifying verification architecture, defining overall reuse methodology, guidelines for detailed feature extraction and verification planning. In addition, you will participate to: developing test environments, creating reusable test cases, running simulations, analyzing and debugging the design, reviewing documents, and creating verification documentation for a SoC/IP block area.