27232 - ASIC Digital Design Engineer

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.



Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.



ASIC Digital Design Engineer



We’re looking for an ASIC Digital Design Engineer to join our DesignWare R&D team in Dublin. This team develops the PCI Express and CXL IP cores used in end-customer applications such as server farms, AI/machine learning, automotive, etc.

As a Senior member of the team you will:

• Define block level specifications and interfaces, collaborating with a diverse team of architects and designers in shaping new product features
• Consistently use best in class design techniques and methodologies to translate your ideas into RTL
• Push your design to the limits of the most advanced technology nodes with unlimited access to state-of-the-art EDA tools
• Build synergies with our verification team to support deep debug, enable coverage closure, and optimize our bug hunting strategies

Key Qualifications

• Proficient in RTL design using Verilog/SystemVerilog
• Familiar with synthesis flows and timing constrains/exceptions
• Usage of scripting languages (TCL, Python, Perl, UNIX shell) to automate repetitive complex tasks
• Experience with Perforce or any other code revision control systems

Preferred Experience

• Typically requires a minimum 5 years of related experience
• Previous experience with reusable and configurable designs
• SystemVerilog Assertions and formal verification techniques
• Experience with on-chip communication protocols like AMBA and layered protocols like PCIe, USB, or Ethernet a plus
• Code and functional coverage closure

Soft skills

• Good written and oral communication skills
• Team player with positive outlook and “can do” attitude
• Ability to work independently and drive results and innovation

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.