Partner-Websites:EURESELA

Verification Architect, DFE ASIC

by:  Nokia Solutions and Networks Oy

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We are looking for Verification Architect to SoC DU organization

Qualifications

We are looking for an engineer with an architect level of experience in RTL verification activities. An engineer who can: define verification strategies and methodologies for projects; plan, coordinate and lead verification people; efficiently utilize System Verilog and UVM in test environment, reuse and VIP development; guide, teach and support less experienced verification engineers in debugging our SoC or IP design and architectures, e.g. in Digital Radio Front End (DFE) area. A person who can lead verification architecture topics in our Digital Front End SoC activities.

 

You have a hungry mind to learn more and you are excited doing a variety of different kinds of design and verification tasks as part of your job. You are always ready to share your knowledge and skills among the people you work with. You are a team worker but also efficient on independent tasks, and your English language skills allow you communicate efficiently in our multicultural environment. You have a passion to develop the best possible verification architecture and ability to establish realistic intermediate steps to achieve the same in phases.

Main Responsibility Area

As a member of SoC DU organization you will participate to verification architecture definition as your main responsibility area. Main responsibilities include: specifying verification architecture, defining overall reuse methodology, guidelines for detailed feature extraction and verification planning. In addition, you will participate to: developing test environments, creating reusable test cases, running simulations, analyzing and debugging the design, reviewing documents, and creating verification documentation for a SoC/IP block area.

Job Description:

  • Technical lead of System-on-Chip verification architecture concepts
  • Definition, implementation and maintenance of efficient verification reuse methodologies
  • Guiding and helping other verification engineers/teams to follow best verification practices
  • Review of functional, design and verification specifications for SoC/IP
  • RTL verification environment and VIP development
  • Prepares and reviews System-on-Chip verification architecture related documentations and applicable documents
  • Cooperate with system engineers, HW/SW development, suppliers and other relevant functions to solve technical issues for quality.
  • Supporting other RTL verification, integration and prototyping teams
  • Support HW/SW Bring-up and debug

Additional Requirements:

  • Master’s Degree in Engineering or equivalent 
  • Over 12 years working experience in RTL verification, in multiple domains, like: IP, Subsystem, SoC
  • Good understanding of digital signal processing and related mathematics
  • Expert with SystemVerilog, UVM and RTL verification domain
  • Understanding VHDL/Verilog language and design debugging methods
  • Understanding of emulation and pre-silicon validation
  • Excellent knowledge of SoC (ASIC/FPGA/low level SW) design and verification tools.
  • Basic understanding of Cellular networks and 2G, 3G, LTE and 5G technology
  • Team and people management experience
  • Fluent spoken and written English
Diese Stelle ist abgelaufen.

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